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SUB Intr_resp
B= SPOLL(70900)
OUTPUT 70900; "STAT:OPER:EVEN?"
ENTER 70900; E
OUTPUT 70900; "DIAG:INTR:RESP?"
ENTER 70900; R
.
.
.
SUBEND
1
Clearing Status The *CLS command clears all status registers (Standard Event Status Register,
Standard Operation Status Event Register, Questionable Data Status Event
Register) and the error queue for an instrument. This clears the corresponding
summary bits (bits 3, 5, & 7) and the instrument-specific bits (bits 0, 1, & 2) in
the Status Byte Register. *CLS does not affect which bits are enabled to be
reflected in the Status Byte Register or enabled to assert SRQ.
1
Interrupting an
External Computer
When a bit in the status byte register is set and has been enabled to assert SRQ
(*SRE command), the instrument sets the GPIB SRQ line true. Interrupts can
be used to alert an external computer to suspend its present operation and find
out what service the instrument requires. (Refer to your computer/language
manuals for information on how to program the computer to respond to the
interrupt.)
To allow any of the status byte register bits to set the SRQ line true, you must
first enable the bit(s) with the *SRE command. For example, suppose your
application requires an interrupt whenever a message is available in the
instrument’s output queue (status byte register bit 4). The decimal weight of this
bit is 16. You can enable bit 4 to assert SRQ by sending:
*SRE 16
NOTE You can determine which bits are enabled in the Status Register using *SRE?.
This command returns the decimal weighted sum of all enabled bits.
6-10 Controlling Instruments Using GPIB