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ADSP-2186
REV. 0
–17–
TIMING PARAMETERS
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
t
CKI
CLKIN Period 60 [50] 150 ns
t
CKIL
CLKIN Width Low 20 ns
t
CKIH
CLKIN Width High 20 ns
Switching Characteristics:
t
CKL
CLKOUT Width Low 0.5 t
CK
– 7 ns
t
CKH
CLKOUT Width High 0.5 t
CK
– 7 ns
t
CKOH
CLKIN High to CLKOUT High 0 20 ns
Control Signals
Timing Requirements:
t
RSP
RESET Width Low
1
5 t
CK
ns
t
MS
Mode Setup Before RESET High 2 ns
t
MH
Mode Setup After RESET High 5 ns
NOTES
Parameters displayed inside brackets [ ] represent preliminary 40 MHz specifications.
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
t
CKOH
t
CKI
t
CKIH
t
CKIL
t
CKH
t
CKL
t
MH
t
MS
CLKIN
CLKOUT
PF(2:0)
*
RESET
*
PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 14. Clock Signals