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PRELIMINARY CY8CNP102B, CY8CNP102E
Document #: 001-43991 Rev. *D Page 3 of 38
Pinouts
Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm)
Table 1. Pin Definitions - 100-Pin TQFP
Pin Number Pin Name
Type
Pin Definition
Digital Analog
1 P0_5 IO IO Analog Column Mux Input and Column Output
2 P0_3 IO IO Analog Column Mux Input and Column Output
3 P0_1 IO I Analog Column Mux Input, GPIO
4P2_7IO GPIO
5P2_5IO GPIO
6 P2_3 IO I Direct Switched Capacitor Block Input
7 P2_1 IO I Direct Switched Capacitor Block Input
8 Vcc Power Supply Voltage
9 DNU Reserved for test modes - Do Not Use
10 DNU Reserved for test modes - Do Not Use
11 DNU Reserved for test modes - Do Not Use
12 DNU Reserved for test modes - Do Not Use
13 DNU Reserved for test modes - Do Not Use
14 NC
Not connected on the die
15 P3_5 IO GPIO
16 EN_W Connect to Pin 26 (EN_W to NV_W)
17 P3_1 IO GPIO
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