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PRELIMINARY CY8CNP102B, CY8CNP102E
Document #: 001-43991 Rev. *D Page 36 of 38
Packaging Information
This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package.
Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation
tool dimensions, refer to the document “PSoC Emulator Pod Dimensions” at http://www.cypress.com/design/MR10161.
Thermal Impedance
Package Diagrams
Figure 15. 100-Pin TQFP - 14 x 14 x 1.4 mm
51-85048 *C
Note
10.* T
J
= T
A
+ POWER x θ
JA
Table 41. Thermal Impedance
Package
[10]
Typical θ
JA
* Typical θ
JC
*
100 TQFP 26.14
o
C/W 5.81
o
C/W
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