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EM78P458/459
OTP ROM
PCRD
M
U
X
IOD
0
1
PDRD
P60 ~ P67
PCWR
DQ
Q
_
CLK
P
R
C
L
PDWR
DQ
Q
_
CLK
P
R
C
L
P
R
C
L
CLK
DQ
Q
_
TI n
PORT
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 8 The Circuit of I/O Port and I/O Control Register for P60~P67
/SLEP
T17
T10
T11
IOCE.1
Interrupt
ENI Instruction
DISI Instruction
Interrupt
(Wake-up from SLEEP)
Next Instruction
(Wake-up from SLEEP)
CLK
CLK
CLK
Q
Q
Q
Q
Q
Q
_
_
_
D
D
D
P
P
P
L
L
L
R
R
R
C
C
C
RE.1
Fig. 9 Block Diagram of Port 6 with Input Changed Interrupt/Wake-up
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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