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EM78P458/459
OTP ROM
4.9 Timer
1. Overview
Timer1 (TMR1) and Timer2 (TMR2) (TMRX) are 10-bit clock counters with programmable prescalers,
respectively. They are designed for the PWM module as baud rate clock generators. TMRX can be
read, written, and cleared at any reset conditions.
2. Function description
Fig. 15 shows TMRX block diagram. Each signal and block are described as follows:
Data BusData Bus
PRD1
Comparator
TMR1X
MUX
Period
Match
T1P0 T1P1
T1EN
PRD2
Comparator
TMR2X
MUX
Period
Match
T2P0 T2P1 T2EN
To PWM1IF
To PWM2IF
reset
reset
1:2
1:8
1:32
Fosc
1:64
1:2
1:8
1:32
Fosc
1:64
*TMR1X = TMR1H + TMR1L;
*TMR2X = TMR2H +TMR2L
Fig. 15 TMRX Block Diagram
Fosc: Input clock.
Prescaler ( T1P0 and T1P1/T2P1 and T2P0 ): Options of 1:2, 1:8, 1:32, and 1:64 are defined by
TMRX. It is cleared when any type of reset occurs.
TMR1X and TMR2X (TMR1H/TWR1L and TMR2H/TMR2L ): Timer X register; TMRX is
increased until it matches with PRDX, and then is reset to 0. TMRX cannot be read.
PRDX ( PRD1 and PRD2 ): PWM period register.
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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