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EM78P458/459
OTP ROM
Data BusData Bus
PRD1
Comparator
Comparator
TMR1H + TMR1L
S
RQ
MUX
Duty Cycle
Match
Period
Match
PWM1
T1P0 T1P1 T1EN
IOC51
PRD2
Comparator
Comparator
S
RQ
MUX
Duty Cycle
Match
Period
Match
PWM2
T2P0 T2P1 T2EN
IOC51
To PWM1IF
To PWM2IF
reset
reset
latch
latch
1:2
1:8
1:32
Fosc
1:64
1:2
1:8
1:32
Fosc
1:64
TMR2H + TMR2L
DT2H
+
DT2L
DT1H
+
DT1L
DL2H + DL2L
DL1H + DL1L
Fig. 13 The Functional Block Diagram of the Dual PWMs
Period
Duty Cycle
DT1 = TMR1
PRD1 = TMR1
Fig. 14 The Output Timing of the PWM
2. Increment Timer Counter ( TMRX: TMR1H/TWR1L or TMR2H/TWR2L )
TMRX are ten-bit clock counters with programmable prescalers. They are designed for the PWM
module as baud rate clock generators. TMRX can be read, written, and cleared at any reset
conditions. If employed, they can be turned down for power saving by setting T1EN bit
[PWMCON<4>] or T2EN bit [PWMCON<5>] to 0.
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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