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Enfora Enabler II-G Assisted GPS
Modem Integration Guide
Figure shows a variation of the connection in Figure 9 External Power Control Signal (no external processor) by
using an external RC circuit to generate a pulse that will allow the processor to enter the RTC deep sleep modes.
This will keep the PWR_CTL_SIGNAL signal low for at least 50ms during startup. To reset the module, power
(BATT) must be cycled, and power must be removed long enough for the RC to discharge.
Figure10 External Power Control Signal (using external RC circuit)
MLG0208PB001 29 Version1.01 – 10/3/2006