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EP-6VBA
Page 4-9
Bank 0/1, 2/3, 4/5 DRAM Timing:
This value in this field is set by the system board manufacturer, depending on
whether the board has paged DRAMs or EDO (extended data output)
DRAMs.
The Choice: Bank 0/1, 2/3, 4/5.
SDRAM Cycle length:
This setting defines the CAS timing parameter of the SDRAM in terms of
clocks.
The default is 3.
2: Provides faster memory performance.
3: Provides better memory compatibility.
SDRAM Bank Interleave:
The item allows you to set how many banks of SDRAM support in your
mainboard.
The Choice: 2 Bank, 4 Bank, Disabled.
DRAM Page-Mode:
The item will active or inactive chipset page registers.
Enabled: Page-Mode Enabled.
Disabled: No page registers update and non Page-Mode operation.
DRAM Fast Decoding:
The item will effective DRAM operation sequential.
DRAM Read Option:
The item will effective DRAM reading CMD sequential.
Memory Hole:
You can reserve this memory area for the use of ISA adaptor ROMs.
The default is Disabled.
Enabled: This field enables the main memory (15~16MB) to remap to ISA
BUS.
Disabled: Normal Setting.
Note: If this feature is enabled you will not be able to cache this
memory segment.