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Example 3: Using the Blackfin Processor Voltage Regulator
2-8 Getting Started with ADSP-BF548 EZ-KIT Lite
3. In the Instruction cache memory drop-down list, select Enable
instruction cache.
4. Click OK to set the new project option. VisualDSP++ will regener-
ate the necessary files to enable the instruction cache when the
program runs.
5. Rebuild the project by selecting Project–>Rebuild Project or by
right-clicking the project name Example_2 in the Project window
and selecting Rebuild Project.
Rerunning the example shows a further reduction in execution time and
core cycles because now both the bubble sort and quick sort are benefiting
from L1 code memory via the instruction cache.
Overlooking data placement can be a mistake in application development.
Accordingly, as a final step in this exercise, we will observe the effect of
placing the two data arrays,
out_b and out_m, in L1 memory. Find the
array definitions in the program’s source file (towards the end, just above
the main() definition) and uncomment the section directives. This will
place the arrays in the L1_data_a section of L1 data memory. Rebuild and
rerun the project, then marvel at the overall program performance
improvement: from 19 seconds down to 1 second or so. Excellent result!
Example 3: Using the Blackfin Processor
Voltage Regulator
Of course, speed is not everything in a high-performance application.
Sometimes the power required to accomplish a task is more important
than the time taken, particularly for mobile devices. Blackfin processors
feature an internal voltage regulator that controls the voltage level at
which the core operates. The supported levels and the corresponding max-
imum core and system clock rates for each level are documented in the
datasheet for each processor.