Filter
Top Products
Example 3: Using the Blackfin Processor Voltage Regulator
2-10 Getting Started with ADSP-BF548 EZ-KIT Lite
Our application (
Sorts.c) looks similar to the application in the previous
example: a work loop in main() repeatedly executes the bubble sort and
quick sort functions. Additional calls at the start and end of main() initial-
ize and terminate the SSL library as mentioned above; additionally, the
work loop is wrapped inside another loop. This new outer loop cycles
through a number of core voltage settings and uses the SSL function
adi_pwr_SetMaxFreqForVolt() to adjust the voltage regulator and set the
clocks to the maximum supported by the new level. Then the loop calls
the adi_pwr_GetFreq() function to get the new clock rates, runs the work
loop, and prints voltage, clock, elapsed time, and cycles values to the Con-
sole window.
Table 2-2 shows typical results from example 3. Since the entire program
is in L1 memory, the Elapsed Seconds column shows a decrease as the
core voltage (and hence the core clock rate) increases, while the number of
cycles executed remains more or less constant. However, the System MHz
column serves as a reminder that for a real application with code and data
in external memory (and perhaps with other peripherals dependant on the
system clock rate), core clock speed is not the only determining factor
when balancing power consumption against speed.
Table 2-2. Typical Results From Example 3
Core Volts Core MHz System MHz Elapsed Seconds Core Cycles
0.85 250.0 83.3 12 2936M
0.95 325.0 81.3 9 2936M
1.05 400.0 100.0 7 2935M
1.25 500.0 125.0 6 2935M