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EM78P809N
8-Bit Microcontroller
Product Specification (V1.0) 07.26.2005
• 9
(This specification is subject to change without further notice)
Bit 3 (P) : Power down bit. Set to “1” during power on or by a "WDTC" command
and reset to “0” by a "SLEP" command.
Bit 2 (Z) : Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC) : Auxiliary carry flag
Bit 0 (C) : Carry flag
R4/RSR − RAM Select Register ( Address: 04h )
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GRBS1 RBS0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0
Bit 7: 6 ( GRBS1 : GRBS0 ) : determine which general purpose banks are
activated among the 4 banks. Use BANK instruction (e.g. BABK 1) to
change bank.
GRBS1 GRBS0 General Purpose Register Bank (Address 20H ~ 3FH)
0 0 Bank 0
0 1 Bank 1
1 0 Bank 2
1 1 Bank 3
Bit 5: 0 ( RSR5 : RSR0 ) : are used to select the registers (address: 00h~3Fh) in
the indirect addressing mode. If no indirect addressing is used, the RSR
can be used as an 8-bit general-purpose read/write register. See the
data memory configuration in Fig. 3.
Register Bank 0 ( R3 bits (7, 6) = (0, 0) )
SCR − System Control Register, Program ROM Page Select ( Address: 05h )
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 PS2 PS1 PS0 0 1 SIS REM
Bit 6 (PS2) ~ 4 (PS0) : ROM Page select bits. User can use PAGE instruction (e.g.
PAGE 1) or set PS2~PS0 bits to change the ROM page. When
executing a "JMP", "CALL", or other instructions which cause the
program counter to change (e.g. MOV R2, A), PS2~PS0 are loaded into
the 13th to 11th bits of the program counter and select one of the
available program memory pages. Note that RET (RETL, RETI)
instruction does not change the PS2~PS0 bits. That is, return will
always be to the page from where the subroutine was called, regardless
of the PS2~PS0 bits current setting.