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CHAPTER 7 HARDWARE SPECIFICATIONS
User's Manual U13502EJ2V0UM00
74
[Pin layout]
Pin IN/OUT Compatible mode ECP mode
1 OUT Busy PeriphAck
2 OUT Select Xflag
3 OUT Nack PeriphClk
4 OUT Nfault nPeriphRequest
5 OUT PError nAckReverse
6 IN/OUT Data 1 (Least Significant Bit)
7 IN/OUT Data 2
8 IN/OUT Data 3
9 IN/OUT Data 4
10 IN/OUT Data 5
11 IN/OUT Data 6
12 IN/OUT Data 7
13 IN/OUT Data 8 (Most Significant Bit)
14 IN Ninit nReverseRequest
15 IN Nstobe HostClk
16 IN NselectIn IEEE1284 active
17 IN NautoFd HostAck
18 IN Host Logic High
19
−
Signal Ground (Busy)
20
−
Signal Ground (Select)
21
−
Signal Ground (nAck)
22
−
Signal Ground (nFault)
23
−
Signal Ground (PError)
24
−
Signal Ground (Data1)
25
−
Signal Ground (Data2)
26
−
Signal Ground (Data3)
27
−
Signal Ground (Data4)
28
−
Signal Ground (Data5)
29
−
Signal Ground (Data6)
30
−
Signal Ground (Data7)
31
−
Signal Ground (Data8)
32
−
Signal Ground (nInit)
33
−
Signal Ground (nStrobe)
34
−
Signal Ground (nSelectIn)
35
−
Signal Ground (nAutoFd)
36 OUT Peripheral Logic High