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Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families 111
Datasheet Volume One of Two
Thermal Management Specifications
reduced frequency and voltage results in a reduction to the processor power
consumption. The second method (clock modulation) reduces power consumption by
modulating (starting and stopping) the internal processor core clocks. The processor
intelligently selects the appropriate TCC method to use on a dynamic basis. BIOS is not
required to select a specific method.
The Adaptive Thermal Monitor feature must be enabled for the processor to be
operating within specifications. Snooping and interrupt processing are performed in
the normal manner while the TCC is active.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would be activated for very short periods of time when running the most power
intensive applications. The processor performance impact due to these brief periods of
TCC activation is expected to be so minor that it would be immeasurable. An under-
designed thermal solution that is not able to prevent excessive activation of the TCC in
the anticipated ambient environment may cause a noticeable performance loss, and in
some cases may result in a T
C
that exceeds the specified maximum temperature which
may affect the long-term reliability of the processor. In addition, a thermal solution that
is significantly under-designed may not be capable of cooling the processor even when
the TCC is active continuously. Refer to the
Intel® Xeon® Processor E5-
1600/2600/4600 v1 and v2 Product Families Thermal / Mechanical Design Guide for
information on designing a compliant thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.
5.2.2.1 Frequency/SVID Control
The processor uses Frequency/SVID control whereby TCC activation causes the
processor to adjust its operating frequency (via the core ratio multiplier) and VCC input
voltage (via the SVID signals). This combination of reduced frequency and voltage
results in a reduction to the processor power consumption.
This method includes multiple operating points, each consisting of a specific operating
frequency and voltage. The first operating point represents the normal operating
condition for the processor. The remaining points consist of both lower operating
frequencies and voltages. When the TCC is activated, the processor automatically
transitions to the new lower operating frequency. This transition occurs very rapidly (on
the order of microseconds).
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new SVID code to the VCC voltage regulator. The
voltage regulator must support dynamic SVID steps to support this method. During the
voltage change, it will be necessary to transition through multiple SVID codes to reach
the target operating voltage. Each step will be one SVID table entry (see Table 7-3,
“VR12.0 Reference Code Voltage Identification (VID)”). The processor continues to
execute instructions during the voltage transition. Operation at the lower voltages
reduces the power consumption of the processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
voltage transition back to the normal system operating point via the intermediate