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Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families 115
Datasheet Volume One of Two
Thermal Management Specifications
to zero, then the processor ignores all external assertions of
MEM_HOT_{C01/C23}_N signals (in effect they become outputs).
• Output Function: The output behavior of the MEM_HOT_{C01/C23}_N signals
supports Level mode. In this mode, MEM_HOT_{C01/C23}_N event temperatures
are programmable via TEMP_OEM_HI, TEMP_LOW, TEMP_MID, and TEMP_HI
threshold settings in the iMC. In Level mode, when asserted, the signal indicates to
the platform that a BIOS-configured thermal threshold has been reached by one or
more DIMMs in the covered channel pair.
5.2.6.4 Integrated Dual SMBus Master Controllers for System Memory
Interface
The processor includes two integrated SMBus master controllers running at 100 KHz for
dedicated PCU access to the serial presence detect (SPD) devices and thermal sensors
(TSoD) on the DIMMs. Each controller is responsible for a pair of memory channels and
supports up to eight SMBus slave devices. Note that clock-low stretching is not
supported by the processor. To avoid design complexity and minimize package C-state
transitions, the SMBus interface between the processor and DIMMs must be connected.
The SMBus controllers for the system memory interface support the following SMBus
protocols/commands:
• Random byte Read
•Byte Write
•I
2
C* Write to Pointer Register
•I
2
C Present Pointer Register Word Read
•I
2
C Pointer Write Register Read.
Refer to the System Management Bus (SMBus) Specification, Revision 2.0 for standing
timing protocols and specific command structure details.
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