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Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families 61
Datasheet Volume One of Two
Interfaces
Note: The 2-byte MSR Address field and read data field defined in Figure 2-43 are sent in standard PECI
ordering with LSB first and MSB last.
2.5.2.7.3 Supported Responses
The typical client response is a passing FCS, a passing Completion Code and valid data.
Under some conditions, the client’s response will indicate a failure.
2.5.2.7.4 RdIAMSR() Capabilities
The processor PECI client allows PECI RdIAMSR() access to the registers listed in
Table 2-11. These registers pertain to the processor core and uncore error banks
(machine check banks 0 through 19). Information on the exact number of accessible
banks for the processor device may be obtained by reading the IA32_MCG_CAP[7:0]
MSR (0x0179). This register may be alternatively read using a RDMSR RBIOS
instruction. Please consult the Intel® Xeon® Processor E5 v2 Prodcut Family
Specification Update for more information on the exact number of cores supported by a
particular processor SKU. Any attempt to read processor MSRs that are not accessible
over PECI or simply not implemented will result in a completion code of 0x90.
Figure 2-43. RdIAMSR()
Table 2-10. RdIAMSR() Response Definition
Response Meaning
Bad FCS Electrical error
Abort FCS Illegal command formatting (mismatched RL/WL/Command Code)
CC: 0x40 Command passed, data is valid.
CC: 0x80 Response timeout. The processor was not able to generate the required response in a timely
fashion. Retry is appropriate.
CC: 0x81 Response timeout. The processor is not able to allocate resources for servicing this command
at this time. Retry is appropriate.
CC: 0x82 The processor hardware resources required to service this command are in a low power state.
Retry may be appropriate after modification of PECI wake mode behavior if appropriate.
CC: 0x90 Unknown/Invalid/Illegal Request
CC: 0x91 PECI control hardware, firmware or associated logic error. The processor is unable to process
the request.