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Advanced Configuration and Power Interface (ACPI)
States Supported
This section describes the ACPI states supported by the processor.
Table 11. System States
State Description
G0/S0 Full On Mode.
G1/S3-Cold
Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the
processor).
G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot.
G3 Mechanical off. All power removed from system.
Table 12. Processor Core / Package State Support
State Description
C0 Active mode, processor executing code.
C1 AutoHALT state.
C1E AutoHALT state with lowest frequency and voltage operating point.
C3
Execution cores in C3 state flush their L1 instruction cache, L1 data cache, and L2 cache
to the L3 shared cache. Clocks are shut off to each core.
C6 Execution cores in this state save their architectural state before removing core voltage.
C7
Execution cores in this state behave similarly to the C6 state. If all execution cores
request C7 state, L3 cache ways are flushed until it is cleared. If the entire L3 cache is
flushed, voltage will be removed from the L3 cache. Power removal to SA, Cores and L3
will reduce power consumption. C7 may not be available on all SKUs.
Table 13. Integrated Memory Controller States
State Description
Power up CKE asserted. Active mode.
Pre-charge
Power-down
CKE de-asserted (not self-refresh) with all banks closed.
Active Power-
down
CKE de-asserted (not self-refresh) with minimum one bank active.
Self-Refresh CKE de-asserted using device self-refresh.
Table 14. PCI Express* Link States
State Description
L0 Full on – Active transfer state.
L0s First Active Power Management low-power state – Low exit latency.
L1 Lowest Active Power Management – Longer exit latency.
L3 Lowest power state (power-off) – Longest exit latency.
4.1
Processor—Power Management
Desktop 4th Generation Intel
®
Core
™
Processor Family, Desktop Intel
®
Pentium
®
Processor Family, and Desktop Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2 December 2013
50 Order No.: 328897-004