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Reset and Miscellaneous Signals
Table 33. Reset and Miscellaneous Signals
Signal Name Description Direction /
Buffer Type
CFG[19:0]
Configuration Signals: The CFG signals have a default value of
'1' if not terminated on the board.
• CFG[1:0]: Reserved configuration lane. A test point may be
placed on the board for these lanes.
• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
• CFG[3]: MSR Privacy Bit Feature
— 1 = Debug capability is determined by
IA32_Debug_Interface_MSR (C80h) bit[0] setting
— 0 = IA32_Debug_Interface_MSR (C80h) bit[0] default
setting overridden
• CFG[4]: Reserved configuration lane. A test point may be
placed on the board for this lane.
• CFG[6:5]: PCI Express* Bifurcation:
1
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
• CFG[19:7]: Reserved configuration lanes. A test point may
be placed on the board for these lands.
I/O
GTL
CFG_RCOMP
Configuration resistance compensation. Use a 49.9 Ω ±1%
resistor to ground.
—
FC_x
FC (Future Compatibility) signals are signals that are available for
compatibility with other processors. A test point may be placed
on the board for these lands.
PM_SYNC
Power Management Sync: A sideband signal to communicate
power management status from the platform to the processor.
I
CMOS
PWR_DEBUG#
Signal is for debug. I
Asynchronous
CMOS
IST_TRIGGER
Signal is for IFDIM testing only. I
CMOS
IVR_ERROR
Signal is for debug. If both THERMTRIP# and this signal are
simultaneously asserted, the processor has encountered an
unrecoverable power delivery fault and has engaged automatic
shutdown as a result.
O
CMOS
RESET#
Platform Reset pin driven by the PCH. I
CMOS
RSVD
RSVD_TP
RSVD_NCTF
RESERVED: All signals that are RSVD and RSVD_NCTF must be
left unconnected on the board. Intel recommends that all
RSVD_TP signals have via test points.
No Connect
Test Point
Non-Critical to
Function
SM_DRAMRST#
DRAM Reset: Reset signal from processor to DRAM devices. One
signal common to all channels.
O
CMOS
TESTLO_x
TESTLO should be individually connected to V
SS
through a
resistor.
Note: 1. PCIe bifurcation support varies with the processor and PCH SKUs used.
6.3
Signal Description—Processor
Desktop 4th Generation Intel
®
Core
™
Processor Family, Desktop Intel
®
Pentium
®
Processor Family, and Desktop Intel
®
Celeron
®
Processor Family
December 2013 Datasheet – Volume 1 of 2
Order No.: 328897-004 85