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assertion with all pages closed). Pre-charge power-down provides greater power
savings, but has a bigger performance impact since all pages will first be closed before
putting the devices in power-down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks, CKE, ODE, and CS signals are controlled per DIMM rank and will be powered
down for unused ranks.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
DRAM Running Average Power Limitation (RAPL)
RAPL is a power and time constant pair. DRAM RAPL defines an average power
constraint for the DRAM domain. Constraint is controlled by the PCU. Platform entities
(PECI or in-band power driver) can specify a power limit for the DRAM domain. PCU
continuously monitors the extant of DRAM throttling due to the power limit and
rebudgets the limit between DIMMs.
DDR Electrical Power Gating (EPG)
The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the
processor is at C3 or deeper power state.
In C3 or deeper power state, the processor internally gates V
DDQ
for the majority of
the logic to reduce idle power while keeping all critical DDR pins such as
SM_DRAMRST#, CKE and VREF in the appropriate state.
In C7, the processor internally gates V
CCIO_TERM
for all non-critical state to reduce idle
power.
In S3 or C-state transitions, the DDR does not go through training mode and will
restore the previous training information.
PCI Express* Power Management
• Active power management is supported using L0s, and L1 states.
• All inputs and outputs disabled in L2/L3 Ready state.
Direct Media Interface (DMI) Power Management
Active power management is supported using L0s/L1 state.
4.3.2.4
4.3.3
4.3.4
4.4
4.5
Power Management—Processor
Desktop 4th Generation Intel
®
Core
™
Processor Family, Desktop Intel
®
Pentium
®
Processor Family, and Desktop Intel
®
Celeron
®
Processor Family
December 2013 Datasheet – Volume 1 of 2
Order No.: 328897-004 63