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Phase Locked Loop (PLL) Signals
Table 37. Phase Locked Loop (PLL) Signals
Signal Name Description Direction / Buffer
Type
BCLKP
BCLKN
Differential bus clock input to the processor I
Diff Clk
DPLL_REF_CLKP
DPLL_REF_CLKN
Embedded Display Port PLL Differential Clock In:
135 MHz
I
Diff Clk
SSC_DPLL_REF_CLKP
SSC_ DPLL_REF_CLKN
Spread Spectrum Embedded DisplayPort PLL
Differential Clock In: 135 MHz
I
Diff Clk
Testability Signals
Table 38. Testability Signals
Signal Name Description Direction / Buffer
Type
BPM#[7:0]
Breakpoint and Performance Monitor Signals:
Outputs from the processor that indicate the status of
breakpoints and programmable counters used for
monitoring processor performance.
I/O
CMOS
DBR#
Debug Reset: This signal is used only in systems where
no debug port is implemented on the system board.
DBR# is used by a debug port interposer so that an in-
target probe can drive system reset.
O
PRDY#
Processor Ready: This signal is a processor output
used by debug tools to determine processor debug
readiness.
O
Asynchronous CMOS
PREQ#
Processor Request: This signal is used by debug tools
to request debug operation of the processor.
I
Asynchronous CMOS
TCK
Test Clock: This signal provides the clock input for the
processor Test Bus (also known as the Test Access
Port). This signal must be driven low or allowed to float
during power on Reset.
I
GTL
TDI
Test Data In: This signal transfers serial test data into
the processor. This signal provides the serial input
needed for JTAG specification support.
I
GTL
TDO
Test Data Out: This signal transfers serial test data out
of the processor. This signal provides the serial output
needed for JTAG specification support.
O
Open Drain
TMS
Test Mode Select: This is a JTAG specification
supported signal used by debug tools.
I
GTL
TRST#
Test Reset: This signal resets the Test Access Port
(TAP) logic. This signal must be driven low during power
on Reset.
I
GTL
6.7
6.8
Signal Description—Processor
Desktop 4th Generation Intel
®
Core
™
Processor Family, Desktop Intel
®
Pentium
®
Processor Family, and Desktop Intel
®
Celeron
®
Processor Family
December 2013 Datasheet – Volume 1 of 2
Order No.: 328897-004 87