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26 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
2.2 PCI Express* Interface
This section describes the PCI Express* 3.0 interface capabilities of the processor. See
the PCI Express* Base Specification for details of PCI Express*
3.0.
2.2.1 PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged. The PCI Express* configuration uses
standard mechanisms as defined in the PCI Plug-and-Play specification.
The PCI Express* architecture is specified in three layers: Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-1 for the PCI Express* Layering Diagram.
PCI Express* uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side, the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
Figure 2-1. PCI Express* Layering Diagram
Transaction
Data Link
Physical
Logical Sub-Block
Electrical Sub-Block
RX TX
Transaction
Data Link
Physical
Logical Sub-Block
Electrical Sub-Block
RX TX
Transaction
Data Link
Physical
Logical Sub-Block
Electrical Sub-Block
RX TX
Transaction
Data Link
Physical
Logical Sub-Block
Electrical Sub-Block
RX TX