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48 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
Power Limit for
the VCC Power
Plane Write /
Read
25 0x0000
Power Limit
Data
N/A
Read power limit
data for VCC power
plane
MSR 638h: PP0_POWER_LIMIT
CSR: PP0_POWER_LIMIT
Package Power
Limits For
Multiple Turbo
Modes
26 0x0000 N/A
Power Limit 1
Data
Write power limit
data 1 in multiple
turbo mode.
MSR 610h:
PACKAGE_POWER_LIMIT
CSR: PACKAGE_POWER_LIMIT
Package Power
Limits For
Multiple Turbo
Modes
27 0x0000 N/A
Power Limit 2
Data
Write power limit
data 2 in multiple
turbo mode.
MSR 610h:
PACKAGE_POWER_LIMIT
CSR: PACKAGE_POWER_LIMIT
Package Power
Limits For
Multiple Turbo
Modes
26 0x0000
Power Limit 1
Data
N/A
Read power limit 1
data in multiple
turbo mode.
MSR 610h:
PACKAGE_POWER_LIMIT
CSR: PACKAGE_POWER_LIMIT
Package Power
Limits For
Multiple Turbo
Modes
27 0x0000
Power Limit 2
Data
N/A
Read power limit 2
data in multiple
turbo mode.
MSR 610h:
PACKAGE_POWER_LIMIT
CSR: PACKAGE_POWER_LIMIT
Package Power
Limit
Performance
Status Read
08
0x00FF - CPU
package
Accumulated
CPU throttle
time
N/A
Read the total time
for which the
processor package
was throttled due to
power limiting.
CSR:
PACKAGE_RAPL_PERF_STATUS
Efficient
Performance
Indicator Read
06 0x0000
Number of
productive
processor cycles
N/A
Read number of
productive cycles for
power budgeting
purposes.
N/A
ACPI P-T Notify
Write & Read
33 0x0000 N/A
New p-state
equivalent of P1
used in
conjunction with
package power
limiting
Notify the processor
PCU of the new p-
state that is one
state below the
turbo frequency as
specified through the
last ACPI Notify
N/A
ACPI P-T Notify
Write & Read
33 0x0000
New p-state
equivalent of P1
used in
conjunction with
package power
limiting
N/A
Read the processor
PCU to determine
the p-state that is
one state below the
turbo frequency as
specified through the
last ACPI Notify
N/A
Caching Agent
TOR Read
39
Cbo Index,
TOR Index,
Bank#;
Read Mode
Caching Agent
(Cbo) Table of
Requests (TOR)
data;
Core ID &
associated valid
bit
N/A
Read the Cbo TOR
data for all enabled
cores in the event of
a 3-strike timeout.
Can alternatively be
used to read ‘Core
ID’ data to confirm
that IERR was
caused by a core
timeout
N/A
Thermal Margin
Read
10 0x0000
Thermal margin
to processor
thermal profile
or load line
N/A
Read margin to
processor thermal
load line
N/A
Table 2-8. RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization
Services Summary (Sheet 3 of 3)
Service
Index
Value
(decimal)
Parameter
Value
(word)
RdPkgConfig()
Data (dword)
WrPkgConfig()
Data (dword)
Description
Alternate Inband
MSR or CSR Access