Intel UPI-C42 Computer Hardware User Manual


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UPI-C42UPI-L42
Table 3 Signature Mode Table
Address
Device No of
Type Bytes
Test CodeChecksum 0 0FH ROMOTP 25
16H 1EH
Intel Signature 10H 11H ROMOTP 2
User Signature 12H 13H OTP 2
Test Signature 14H 15H ROMOTP 2
Security Byte 1FH or 3FH ROMOTP 2
UPI-C42 Intel Signature 20H 21H ROMOTP 2
User Defined UPI-C42 OTP EPROM Space 22H 3EH ROMOTP 30
ACCESS CODE
The following table summarizes the access codes required to invoke the Sync Mode Signature Mode
and the Security Bit respectively Also the programming and verification modes are included for
comparison
Control Signals Data Bus
Access Code
Modes Port 2 Port 1
T0 RST SS EA PROG V
DD
V
CC
0123456701230 1234567
Programming 0 0 1 HV 1 V
DDH
V
CC
Address Addr a
0
a
1
XXXXXX
Mode
0 1 1 HV STB V
DDH
V
CC
Data In Addr
Verification 0 0 1 HV 1 V
CC
V
CC
Address Addr a
0
a
1
XXXXXX
Mode
111HV1V
CC
V
CC
Data Out Addr
Sync Mode STB 0 HV 0 X V
CC
V
CC
XXXXXXXXXXX XXXXXXXX
High
Signature Prog 0 0 1 HV 1 V
DDH
V
CC
Addr (see Sig Mode Table) 0 0 0 0 1 1 1 1 X X 1
Mode
0 1 1 HV STB V
DDH
V
CC
Data In 0 0 0
Verify 0 0 1 HV 1 V
CC
V
CC
Addr (see Sig Mode Table) 0 0 0
111HV1V
CC
V
CC
Data Out 0 0 0
Security Prog 0 0 1 HV 1 V
DDH
V
CC
Address 0 0 0
BitByte
0 1 1 HV STB V
DDH
V
CC
Data In 0 0 0
Verify 0 0 1 HV 1 V
CC
V
CC
Address 0 0 0
111HV1V
CC
V
CC
Data Out 0 0 0
NOTE
1 a
0
e
0or1a
1
e
0or1a
0
must
e
a
1
12
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