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B-16 October 22, 1999 SP Switch Router Adapter Guide - 1.4 Update 2
Log Messages
Message descriptions
DESCRIPTION: This message is logged when the TX-CPU detects that the TC has
detected a parity error on the TBUS. This is a fatal error, the card is reset and reloaded
automatically. If the problem persists, reset/replace the card. int1 is the content of the
TC’s interrupt register.
“Timeout waiting for CFG_DN bits clear, stat0=%x.”
LOG_FILE: /var/log/gr.console
SOURCE_FILE: rx/tbsi_fpga.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: FATAL
DESCRIPTION: This message is logged when the SP Switch Router Adapter card fails to
program the FPGAs. Replace the card. stat0 is the content of the hardware status
register.
“Timeout waiting for FPGA_INIT_COMPLETE, stat0=%x.”
LOG_FILE: /var/log/gr.console
SOURCE_FILE: rx/tbsi_fpga.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: FATAL
DESCRIPTION: This message is logged when the FPGAs fail to complete their power
on/reset initialization sequence. Replace the card. stat0 is the content of the hardware
status register.
“RX: got TBIC INITED fron TX.”
LOG_FILE: /var/log/gr.console
SOURCE_FILE: rx/tbsi_ipc.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: INFO
DESCRIPTION: This message is logged when the TX-CPU has initialized the Transmit
TBIC.
“RX: Port connected, stat=0x%x.”
LOG_FILE: /var/log/gr.console
SOURCE_FILE: rx/tbsi_rc.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: INFO
DESCRIPTION: This message is logged when the Receive TBIC’s receive port is
connected to the switch chip’s Send port.