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Chapter 4 – SocketModem Parallel Interface – A Programmer's Description
Multi-Tech Systems, Inc. SocketModem MT5600SMI Developer’s Guide 19
Table 4–1. Parallel Interface Registers
BIT No.
Register
No.
Register
Name
7 6 5 4 3 2 1 0
7 Scratch Register (SCR) Scratch Register
6 Modem Status Register
(MSR)
Data
Carrier
Detect
(DCD)
Ring
Indicator
(RI)
Data Set
Ready
(DSR)
Clear to
Send CTS)
Delta Data
Carrier
Detect
(DDCD)
Trailing
E
dge of Ring
Indicator
(TERI)
Delta Data
Set Ready
(DDSR)
Delta Clear
to Send
(DCTS)
5 Line Status Register
(LSR)
RX
FIFO
Error
Transmitter
Empty
(TEMT)
Transmitter
Buffer
Register
Empty
(THRE)
Break
Interrupt
(BI)
Framing
Error
(FE)
Parity
Error
(PE)
Overrun
Error
(OE)
Receiver
Data
Ready
(DR)
4 Modem Control
Register (MCR)
0 0 0 Local
Loopback
Out 2 Out 1 Request
to Send
(RTS)
Data
Terminal
Ready
(DTR)
3 Line Control Register
(LCR)
Divisor
Latch
Access Bit
(DLAB)
Set
Break
Stick
Parity
Even
Parity
Select
(EPS)
Parity
Enable
(PEN)
Number
of Stop
Bits
(STB)
Word
Length
Select
Bit 1
(WLS1)
Word Length
Select
Bit 0
(WLSO)
2 Interrupt Identify
Register (IIR)
(Read Only)
FIFOs
Enabled
FIFOs
Enabled
0 0 Pending
Interrupt ID
Bit 2
Pending
Interrupt ID
Bit 1
Pending
Interrupt ID
Bit 0
“0” if
Interrupt
Pending
2 FIFO Control Register
(FCR)
(Write Only)
Receiver
Trigger
MSB
Receiver
Trigger
LSB
Reserved Reserved DMA
Mode
Select
TX FIFO
Reset
RX FIFO
Reset
FIFO
Enable
1
(DLAB = 0)
Interrupt Enable
Register (ER)
0 0 0 0 Enable
Modem
Status
Interrupt
(EDSSI)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Enable
Received
Data
Available
Interrupt
(ERBFI)
0
(DLAB = 0)
Transmitter Buffer
Register
(THR)
Transmitter FIFO Buffer Register (Write Only)
0
(DLAB = 0)
Receiver Buffer
Register (RBR)
Receiver FIFO Buffer Register (Read Only)
1
(DLAB = 1)
Divisor Latch MSB
Register (DLM)
Divisor Latch MSB
0
(DLAB = 1)
Divisor Latch LSB
Register (DLL)
Divisor Latch LSB