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DDR3THIN-MN-XXX 54 Doc. Rev. 1.11
Figure 4 - Read Data Latency = CAS Latency + CAS Additive Latency + RDIMM (5+0+1) = 6 cycles)
5.6 Selecting B_DDR3D_XX Write Data Sample Points
Unlike valid DDR Read data, valid Write data is bisected by the Strobes. Since valid DDR3
Write data is bisected by the Strobes (see Figure 5) the Setup & Hold sample point must be set
for the valid data that occurs closest to the clock edge. The appropriate clock edge for Writes is
determined by counting the number of clock cycles specified by the Write Latency MRS value
from the Write Command to the first valid Write Data. (If these values are not known the
technique described in Section 7.3 can be used to determine them.) In Figure 5 the total Write
latency is 6 cycles (Write Latency plus the additional one cycle delay for RDIMM memory).
Figure 5 - Write Data Latency = CAS Write Latency + RDIMM (5+1) = 6 cycles
Sample Pt. #1
Sample Pt. #2
Sample Pt. #1
Sample Pt. #2
Write Data
Preamble