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M16C/26 Group
Rev.0.90 2003.12.28 page 9 of 28
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.5.1.2 Timer A (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, “FFFF16” can be read in underflow, while reloading, and “000016” in overflow.
When setting TAi register to a value during a counter stop, the setting value can be read before a
counter starts counting. Also, if the counter is read before it starts counting after a value is set in the
TAi register while not counting, the set value is read.
_______ _____
3. If a low-level signal is applied to the P85/NMI/SD pin when the TB2SC register IVPCR1 bit = “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
1.5 Precautions for Timers