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M16C/26 Group
Rev.0.90 2003.12.28 page 15 of 28
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.6 Precautions for Serial I/O (Clock-synchronous Serial I/O)
1.6 Precautions for Serial I/O (Clock-synchronous Serial I/O)
1.6.1 Transmission/reception
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1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes
to “L” when the data-receivable status becomes ready, which informs the transmission side that the
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reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if
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the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and
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reception data with consistent timing. With the internal clock, the RTS function has no effect.
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2. If a low-level signal is applied to the P85/NMI/SD pin when the TB2SC register IVPCR1 bit = “1” (three-
_____ _________
phase output forcible cutoff by input on SD pin enabled), the RTS2 and CLK2 pins go to a high-imped-
ance state.