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M16C/26 Group
Rev.0.90 2003.12.28 page 24 of 28
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.10 Precautions for Flash Memory Version
1.10.12 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
1.10.13 Regarding Programming/Erasure Times and Execution Time
As the number of programming/erasure times increases, so does the execution time for software com-
mands (Program, and Block Erase). Especially when the number of programming/erasure times ex-
ceeds 1,000, the software command execution time is noticeably extended. Therefore, the software
command wait time that is set must be greater than the maximum rated value of electrical characteristics.
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The software commands are aborted by hardware reset 1, hardware reset 2, NMI interrupt, and watchdog
timer interrupt. If a software command is aborted by such reset or interrupt, the block that was in process
must be erased before reexecuting the aborted command.
1.10.14 Definition of Programming/Erasure Times
"Number of programs and erasure" refers to the number of erasure per block.
If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times.
For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different
address, this is countedas one program and erasure. However, data cannot be written to the same
adrress more than once without erasing the block. (Rewrite prohibited)
1.10.15
Flash Memory Version Electrical Characteristics 10,000 E/W cycle products (D7, D9, U7, U9)
When Block A or B E/W cycles exceed 100 (D7, D9, U7, U9), select one wait state per block access.
When FMR17 is set to "1", one wait state is inserted per access to Block A or B - regardless of the value
of PM17. Wait state insertion during access to all other blocks, as well as to internal RAM, is controlled by
PM17 - regardless of the setting of FMR17.
To use the limited number of erasure efficiently, write to unused address within the block instead of
rewite. Erase block only after all possible address are used. For example, an 8-word program can be
written 128 times before erase becomes necessary.
Maintaining an equal number of erasure between Block A and B will also improve efficiency.
We recommend keeping track of the number of times erasure is used.
1.10.16 Precaution of Boot Mode
The value which isn't fixed is sometimes output in the I/O port until an internal power supply becomes
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stable when "H" is input to the CNVSS pin and "L" is input to the RESET pin under condition that a internal
power supply isn't stable at the time of the power supply injectiopn.
When setting the CNVSS pin to "H", the following settings are required:
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(1) Apply an "L" signal to the RESET pin and the CNVSS pin.
(2) The VCC is more than 2.7V, and wait beyond ec 2msec.
(Internal power supply stable waiting time)
(3) Apply an "H" signal to the CNVSS pin.
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(4) Apply an "H" signal to the RESET pin.