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M16C/26 Group
Rev.0.90 2003.12.28 page 11 of 28
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.5.1.4 Timer A (Pulse Width Modulation Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.
3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
_______ _____
4. If a low-level signal is applied to the P85/NMI/SD pin when the TB2SC register IVPCR1 bit = “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
1.5 Precautions for Timers