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M16C/26 Group
Rev.0.90 2003.12.28 page 20 of 28
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.8 Precautions for A-D Converter
8. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
• When operating in one-shot or single-sweep mode
Check to see that A-D conversion is completed before reading the target ADi register. (Check the
ADIC register’s IR bit to see if A-D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A-D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit to
“0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The contents of
ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.