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M16C/26 Group
Rev.0.90 2003.12.28 page 17 of 28
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.6.3 Reception
1. In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix set-
tings for transmission even when using the device only for reception. Dummy data is output to the
outside from the TxDi pin when receiving data.
2. When an internal clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 (transmission enabled)
and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an
external clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 and write dummy data to the
UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi input pin.
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the UiC1 register (i = 0 to 2)’s RE bit = “1” (data present in the UiRB register), an overrun
error occurs and the UiRB register OER bit is set to “1” (overrun error occurred). In this case, because
the content of the UiRB register is indeterminate, a corrective measure must be taken by programs on
the transmit and receive sides so that the valid data before the overrun error occurred will be retransmit-
ted. Note that when an overrun error occurred, the SiRIC register IR bit does not change state.
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
5. When an external clock is selected, the conditions must be met while if the CKPOL bit = “0”, the
external clock is in the high state; if the CKPOL bit = “1”, the external clock is in the low state.
• The RE bit of UiC1 register= “1” (reception enabled)
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register= “0” (data present in the UiTB register)
1.6 Precautions for Serial I/O (Clock-synchronous Serial I/O)