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M16C/26 Group
Rev.0.90 2003.12.28 page 21 of 28
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.9 Precautions for Programmable I/O Ports
1.9 Precautions for Programmable I/O Ports
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1. If a low-level signal is applied to the P85/NMI/SD pin when the TB2SC register IVPCR1 bit = “1” (three-
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phase output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to a high-
impedance state.
2. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither
“high” nor “low”), the input level may be determined differently depending on which side—the program-
mable input/output port or the peripheral function—is currently selected.
3. When three phase motor control function is enabled, it becomes the following when "L" is input to the
P85 pin. When you don't want to do such a change, without using the P85 pin as a programable I/O port,
input "H" to the P85 pin before setting PD85 = "L".
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•When the TB2SC register IVPCR1 bit = “1” (three-phase output forcible cutoff by input on SD pin
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enabled), the U/ U/ V/ V/ W/ W pins go to a high-impedance state.
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•When the TB2SC register IVPCR1 bit = “0” (three-phase output forcible cutoff by input on SD pin
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disabled), the U/ U/ V/ V/ W/ W pins go to a normal port.