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M16C/26 Group
Rev.0.90 2003.12.28 page 19 of 28
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1.8 Precautions for A-D Converter
1.8 Precautions for A-D Converter
1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A-D conversion is stopped (before
a trigger occurs).
2. When the VCUT bit of ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref con-
nected), start A-D conversion after passing 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7)) each and the AVSS pin.
Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 1.8.1 is an example connec-
tion of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit for
___________
the ADTRG pin is set to “0” (input mode).
5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)
6. The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.
7. When changing an A-D operation mode, select analog input pin again in the CH2 to CH0 bits of
ADCON0 register and the SCAN1 to SCAN0 bits of ADCON1 register.
Figure 1.8.1. Use of capacitors to reduce noise
Microcomputer
Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
V
CC
V
SS
AV
CC
AV
SS
V
REF
ANi
C4
C1
C2
C3
ANi: ANi (i=0 to 7)
V
CC
V
CC