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10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C 67 Revision 1.91 (08-18-08)
DATASHEET
8.23 Bank 3 - Management Interface
MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0).
MDO - MII Management output. The value of this bit drives the MDO pin.
MDI - MII Management input. The value of the MDI pin is readable using this bit.
MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.
MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-
stated.
The purpose of this interface, along with the corresponding pins is to implement MII PHY management
in software.
8.24 Bank 3 - Revision Register
CHIP - Chip ID. Can be used by software drivers to identify the device used.
REV - Revision ID. Incremented for each revision of a given device.
OFFSET NAME TYPE SYMBOL
8
MANAGEMENT
INTERFACE READ/WRITE MGMT
HIGH
BYTE
Reserved MSK_
CRS100
Reserved Reserved Reserved Reserved Reserved Reserved
00110011
LOW
BYTE
Reserved MDOE MCLK MDI MDO
001100MDI Pin0
OFFSET NAME TYPE SYMBOL
A REVISION REGISTER READ ONLY REV
HIGH
BYTE
00110011
LOW
BYTE
CHIP REV
10010010