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10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.91 (08-18-08) 96 SMSC LAN91C111 REV C
DATASHEET
STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111 can
be read or written until the EEPROM operation completes and both bits are clear. This mechanism is
also valid for reset initiated reloads.
Note: If no EEPROM is connected to the LAN91C111, for example for some embedded applications,
the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted.
Configuration, Base, and Individual Address assume their default values upon hardware reset
and the CPU is responsible for programming them for their final value.