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10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C 91 Revision 1.91 (08-18-08)
DATASHEET
Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected)
TXEMPTY INTR
Write Acknowledge Reg. with
TXEMPTY Bit Set
Read TXEMPTY & TX INTR
Acknowledge TXINTR
Re-Enable TXENA
Return to ISR
Issue "Release" Command
Restore Packet Number
TXEMPTY = 0
&
TXINT = 0
(Waiting for Completion)
TXEMPTY = X
&
TXINT = 1
(Transmission Failed)
TXEMPTY = 1
&
TXINT = 0
(Everything went through
successfully)
Read Pkt. # Register & Save
Write Address Pointer
Register
Read Status Word from RAM
Update Statistics
Update Variables