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Chapter 3: Installation
3-33
JPI2C1
FAN4
FAN6
FAN1
FAN2
J120
LED7
IPMB
UIOP
LED6
LED3
LED2
JWF1
SP1
JF1
I-SATA0
I-SATA1
I-SATA2
I-SATA3
I-SATA4
I-SATA5
JPW1
JPW3
X8DTU-6F+
JPTLAN
JPS1
JPG1
JWD1
TPM
JI2C1
JI2C2
JL1
JOH1
SAS4~7
SAS0~3
LED1
SAS BBU
Battery
USB0/1
USB7
USB6
USB4/5
COM2
UID
TLAN2
LAN2
IPMI_LAN
KB/MOUSE
FAN8/CPU1
FAN7/CPU2
P2-DIMM1C
P2-DIMM2C
P2-DIMM3C
P1-DIMM2C
P1-DIMM1C
P1-DIMM3C
J2: PCI-E 2.0 X16
P1-DIMM3B
P1-DIMM3A
P1-DIMM1A
P1-DIMM1B
P1-DIMM2B
P1-DIMM2A
P2-DIMM3A
P2-DIMM3B
P2-DIMM2A
P2-DIMM2B
P2-DIMM1A
CPU2
P2-DIMM1B
CPU1
LAN1
TLAN1
PHY
JPW2
T-SGPIO1
BIOS
COM1
VGA
JPL1
J1: PCI-E 2.0 X4 (in X16)
LED5
LED4
JBT1
T-SGPIO2
FAN5
FAN3
LAN 1/2
CTRL
10 Gb LAN 1/2
CTRL
BMC
CTRL
IOH 36D
Intel 82576
Intel 82599
Intel
ICH 10R
Intel
SAS
CTRL
LSI 2108
(10Gb LAN1)
(10Gb LAN2)
A
A. TPM Connector
Trusted Platform Module Header
A Trusted Platform Module (TPM)
header is located next to the COM2
connection. This header provides
TPM support to ensure data integrity
and system security. Refer to the
table on the right for pin defi nitions.
Trusted Platform Module (TPM) Header
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
1 LPC Clock 2 GND
3 LPC FRAME# 4 Key
5 LPC Reset# 6 +5V (X)
7 LAD3 8 LAD2
9 +3.3V 10 LAD1
11 LAD0 12 GND
13 SCL 14 SDAT
15 +3V_DUAL 16 SERIRQ (X)
17 GND 18 CLKRUN(X)
19 LPCPD# (X) 20 LDRQ#(X)
Notes:
(X)=TPM does not use the signals.
SCL, SDAT are I
2
C bus clock and data.