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Adapter Host Registers
A-20
If ADR_SEL[1::0] = 00, the 32 LSBs of the 68-bit word are accessed.
If ADR_SEL[1::0] = 01, the middle 32 bits of the 68-bit word are accessed.
If ADR_SEL[1::0] = 1X, the four MSBs of the 68-bit word are accessed (in
the four LSBs of DIO_DATA).
PCI bus-byte enables are honored in writes to the internal RAM; individual byte
writes are allowed. If autoincrement mode is enabled, only the row address in-
crements; the word address is not affected.
A.2.5 DIO Data Register–DIO_DATA @ Base_Address + 12 (Host)
The DIO_DATA register address allows indirect access to internal
ThunderLAN registers and SRAM. There is no actual DIO_DATA register; ac-
cesses to this address are mapped to an internal bus access at the address
specified in the DIO_ADR register.
The DIO_DATA location uses 32-bit PCI data transfers with full-byte control,
following the normal
PCI Local Bus Specification
conventions. ThunderLAN
uses the target-ready (PTRDY#) signal to insert PCI wait states and to ensure
correct data transfers.
Writes to this register cause control of the EEPROM interface pins to go to the
NetSio register. Control of the EEPROM interface swaps between the PCI
NVRAM register and the NetSio register on a most-recently-written basis.
Whenever the PCI NVRAM register is written to, it takes control of the
EEPROM interface pins. Whenever the DIO_DATA register is written to, the
NetSio register takes control of the EEPROM interface pins.