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MII PHY Registers
2-17
ThunderLAN Registers
is 0x1F. When the internal PHY for 10Base-T is used in a standalone mode,
that is, when run from another controller through the MII pins, it is at address
0x00. These are the only two addresses allowed for the internal PHY.
The 100VG-AnyLAN PMI device, the TNETE211, is used to attach 802.12
physical media dependent (PMD) devices to ThunderLAN’s MII. The
TNETE211 has five external pins (DEVSEL[4::0]) that program the address to
which it will respond. If multiple PHYs are used, each must be installed with
a unique address.
Before reading or writing to any PHY register, the MII serial interface must be
synchronized. This involves a one-time write of 32, 1 bits on the MDIO pin.
Once this is done, an access can be done with a two-bit start delimiter, then
a two-bit op code (for read or write), followed by five bits of PHY address, five
bits of register address, two bits of turnaround time in case the PHY is going
to write to the data line, and 16 bits of data.
The synchronization code could be done this way:
//––––––––––––––––––––––––––––––––––––––––––––––––––––––––
// MIISync() – send MII synchronization pattern to all
// possible MII interfaces
//
// Parameters:
// base_addr base address on TLAN internal registers
//
// Return val:
// none
//––––––––––––––––––––––––––––––––––––––––––––––––––––––––
void MIISync(WORD base_addr)
{
register int i;
clr(MTXEN);
where clr is a macro to set a bit to 0 in the
NetSio
internal register. In this case,
bit MTXEN in NetSio is cleared.
#define clr(x)
DioWrByte(base_addr,Net_Sio,(BYTE)(DioRd
Byte(base_addr,Net_Sio)&~x))
When the output enable bit is cleared and the PHYs have just been turned on,
none of them outputs data. The value on the data line is determined by the pull-