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Host Registers
2-10
To enable reads of adjacent addresses without reposting the address, bit 15
of the DIO_ADR register can be set, which causes the address to be post-in-
cremented by 4 after each access of the DIO_DATA register. This function is
useful when reading the statistics or reading the internal SRAM. Autoincre-
menting while reading the FIFO memory causes a move to the same part of
the next 68-bit word; it does not move to the next part of the same 68-bit word.
The two least significant bits (LSBs) of the DIO_ADR must be expressly set
to get to the various parts of each 68-bit entity.
The host registers are addressed either as memory or I/O ports. The PCI con-
figuration space has locations for the O/S to assign up to six memory or I/O
base addresses. The depth of the space requested for each base register im-
plemented is determined by the number of bits, starting at the LSBs, whose
values are fixed. The O/S writes to the rest of the bits (with the assumption that
the fixed positions are equal to 0) at the beginning address of that block.
As an example, the LSB determines whether the base register is a memory
(0) or an I/O space (1) base register. ThunderLAN’s PCI interface reserves
memory I/O space by implementing an I/O and a memory configuration base
register, both with the four LSBs in these registers fixed to indicate the field
width requested be reserved in the respective address space for the host reg-
ister block (four quad words or 16 bytes). The rest of the bits of a base register
are filled in by the O/S after all the space requests are considered.
Assigning space in this way assures that all starts of fields are naturally aligned
to long words or better. It is important to note that by the time either the BIOS
code or driver code is allowed to run, the O/S has queried the card and as-
signed the base addresses. The host registers can be accessed equally in
both address spaces on host processor systems that support both.
Some processors only support memory spaces; in these cases the I/O spaces
are assigned a 0, which is not a valid base register value for a peripheral. The
driver must check for a 0 base offset value before using the I/O method of
accessing the ThunderLAN registers. The base offset must be constant be-
tween host processor resets, but can be different for each execution of the pro-
gram. All host register accesses are done relative to the value found in the re-
spective configuration base register.
The unimplemented base registers in the configuration space return all 0s on
a read. This is equivalent to requesting a 2
32
-byte data space—all of the avail-
able address space in a 32-bit address system. PCI interprets an all-bits-fixed
situation as not implemented.