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reserves the following two LED locations for its drivers. The bit numbers refer
to their locations in LEDreg.
Bit 0 (LSB) displays link status.
Bit 4 displays activity.
2.6.3 EEPROM
The implementation-specific configuration information is read or written into
the EEPROM from two sources. Control of the two-wire serial bus to the
EEPROM (EDIO and EDCLK bits) on reset (hardware or software) rests with
the four bits in the PCI_ NVRAM register (DATA, DDIR, CLOCK, CDIR) in the
PCI configuration space. Any time this register is written to, control of the
EDIO/EDCLK bus reverts back to this register.
The other possible source of values for this bus is from an internal register, the
network serial I/O register NetSio. Here the three bits used to control the inter-
face are EDATA, ETXEN, and ECLOK. The PCI_ NVRAM register interface to
this external EEPROM port was designed assuming that there might be anoth-
er master device on this bus. Note that NetSio does not implement a clock
direction register. Assuming that only one EEPROM is on the serial bus and
only the ThunderLAN device is driving the bus, both control implementations
are equivalent. Use NetSio when possible to read or write to the EEPROM.