Toshiba PRO500 Laptop User Manual


 
Chapter 1 Hardware Overview
Satellite P500 and Satellite Pro500 Maintenance Manual (960-Q08)
8
BIOS ROM (Flash memory)
16Mbit
Chipset (Montevina Platform)
This gate array has the following elements and functions.
North Bridge (Intel PM45,GM45/GL40)
Merom-M processor System Bus support
DRAM Controller : DDRII 667/800 support
DMI
1299-ball 35 x 35mm Mirco FC-BGA Package
South Bridge (Intel 82801HBM ICH9-M)
Direct Media Interface (DMI)
PCI Express
Serial ATA (SATA) Controller
PCI Interface
Low Pin count (LPC) interface
Serial Peripheral Interface (SPI)
DMA controller
Advanced Programmable Interrupt Controller (APIC)
USB Controllers
Gigabit Ethernet Controller
RTC
GPIO
Enhanced Power Management
SMBus 2.0
High Definition Audio Controller
676-pin 31mmx31mm mBGA Package
Other main system chips
Clock Generator (Montevina Platform: ICS9LPRS365BGLF)
EC/KBC –[W/CIR(Winbond WPCE775CA0DG)] –[WO/CIR(Winbond
WPCE775LA0DG)]
HD Audio (CONEXANT CX20583-10Z)