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PCI-X v5.1 165 Getting Started Guide www.xilinx.com 21
UG158 March 24, 2008
Device Initialization
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Device Initialization
Immediately after FPGA configuration, both the core interface and the user application are
initialized by the startup mechanism present in all Virtex devices. During normal
operation, the assertion of RST# on the PCI-X bus reinitializes the core interface and three-
state all PCI-X bus signals. This behavior is fully compliant with the PCI Local Bus
Specification. The core interface is designed to correctly handle asynchronous resets.
Typically, the user application must be initialized each time the core interfacee is
initialized. In this case, use the RST output of the core interface as the asynchronous reset
signal for the user application. If part of the user application requires an initialization
capability that is asynchronous to PCI-X bus resets, simply design the user application
with a separate reset signal.
Note that these reset schemes require the use of routing resources to distribute reset
signals, since the global resource is not used. The use of the global reset resource is not
recommended.
Configuration Pins
Designers should be aware that PCI-X bus interface pins should not be placed on the dual
purpose I/O pins used for configuration. Please verify the selected UCF to ensure that the
pins do not conflict with the pins used for the chosen configuration mode. It is fine for PCI-
X pins to be located on dual purpose I/O configuration pins that are NOT also used for
configuration. Please refer to the appropriate device pin-out guide for locations of
configuration pins.
Bus Width Detection
A core interface that provides a 64-bit datapath needs to know if it is connected to a 64-bit
bus or a 32-bit bus. The core interface is capable of sensing and adjusting to the bus width
automatically. However, this behavior can be manually forced by setting options in the
HDL configuration file. For more information, see the Initiator/Target for PCI-X User Guide,
and the following section about bus mode detection.
Bus Mode Detection
A core interface that provides backward compatibility with PCI mode must determine
whether it is in PCI-X bus mode or PCI bus mode. The core interface is capable of sensing
and adjusting to the bus mode automatically. However, this behavior can be manually
forced by setting options in the HDL configuration file. See the Initiator/Target for PCI-X
User Guide for details.
The core interface targeting Virtex-E devices cannot support PCI-X bus mode and PCI bus
mode with a single bitstream. This is because the Virtex-E DLL, (required in PCI-X but
forbidden in PCI) cannot be switched on and off by any means other than uploading a new
bitstream to the device. For this reason, a fully compliant design requires two bitstreams
and the ability to reconfigure the FPGA after the bus mode is detected. The core
interfacetargeting Virtex-II and Virtex-II Pro devices can support PCI-X bus mode and PCI
bus mode with a single bitstream, although dual bitstreams may be required in certain
configurations.
For designs that use multiple bitstreams, the RTR output of the core interface will assert
following the deassertion of the bus reset signal if the interface recognizes that the incorrect