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24 www.xilinx.com PCI-X v5.1 165 Getting Started Guide
UG158 March 24, 2008
Chapter 3: Family Specific Considerations
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Input Delay Buffers
Input delay buffers are used to provide guaranteed hold time on all bus inputs when in
PCI bus mode. Where possible, the core interface targeting Virtex devices uses input delay
elements present in the IOBs of the FPGA device. The use of these delay buffers is selected
through the implementation specific constraints file.
Virtex-4 FPGA implementations that support PCI bus mode make use of the new IDELAY
input delay buffer primitives. An IDELAY input delay buffer is a calibrated and adjustable
delay line. This delay mechanism provides superior performance over the legacy input
delay buffers.
Designs that use IDELAY primitives also require the use of the IDELAYCTRL primitive.
The function of the IDELAYCTRL primitive is to calibrate the IDELAY delay lines. To
perform this calibration, the IDELAYCTRL primitive requires a 200 MHz input clock. The
design and wrapper files for use with reference clocks contain IDELAY instances,
IDELAYCTRL instances, and an additional input, REF_I, for a 200 MHz reference clock
from an I/O pin. This reference clock is distributed to all applicable IDELAYCTRL
primitives using a global clock buffer. It is important to note that there is some flexibility in
the origin, generation, and use of this 200 MHz reference clock. The provided design and
wrapper files represent a trivial case that can may be modified to suit specific design
requirements.
• For designs requiring IDELAY and IDELAYCTRL for other IP cores, or custom user
logic, the 200 MHz reference clock can be shared. It is possible to tap the reference
clock in the wrapper file, after it is driven by the global buffer. This signal may be
used by other IDELAY and IDELAYCTRL instances.
• For designs that already have a 200 MHz reference clock distributed on a global clock
buffer, this clock can be shared. The wrapper file can be modified to remove the
external I/O pin and the global clock buffer instance. Simply tap the existing 200 MHz
clock signal and bring it into the wrapper file for the interface to use.
• For designs that do not have a 200 MHz reference clock, it may be possible to generate
a 200 MHz reference clock using a Digital Clock Manager (DCM) and another clock.
The other clock may be available internally or externally, but must be fixed frequency.
In this case, it is the responsibility of the user to verify the following:
1. The jitter of the source clock, to determine if it is appropriate for use as an input to
a DCM.
2. The DCM configuration, to generate a 200 MHz clock on any appropriate DCM
output (CLKFX, CLKDV, and so forth).
3. The jitter of the derived 200 MHz reference clock, to determine if it is appropriate
for use as an input to an IDELAYCTRL.
4. The IDELAYCTRL reset must be tied to the DCM lock output so that the
IDELAYCTRL remains in reset until the DCM is locked.
For more information about timing parameters, see the Virtex-4
FPGA Data Sheet and
Virtex-4 FPGA User Guide. As with the other implementation options, the derived 200 MHz
reference clock must be distributed by a global clock buffer to the IDELAYCTRL instances.
Warning! The fixed frequency requirement of the source clock precludes the use of the PCI
bus clock, unless the design is used in an embedded/closed system where the PCI bus
clock is known to be a fixed frequency. See “Bus Clock Usage” for additional information
about the allowed behavior of the PCI bus clock in compliant systems.