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28 www.xilinx.com PCI-X v5.1 165 Getting Started Guide
UG158 March 24, 2008
Chapter 4: Functional Simulation
R
../../src/xpci/pcix_lc.v
../../src/xpci/pcix_core.v
+libext+.vmd+.v
-y <Xilinx Install Path>/verilog/src/unisims
-y <Xilinx Install Path>/verilog/src/simprims
This subset list does not include any configuration file, user application, top-level
wrapper, or test bench. These additional files are required for a meaningful simulation.
5. To run the IUS simulation, type the following:
ncverilog -f test_tb.f
IUS processes the simulation files and exits. The test bench prints status messages to
the console.
6. After completing simulation, view the ncverilog.log file to check for errors.
The Simvision browser may be used to view the simulation results.
7. If desired, start Simvision using the following command:
simvision
Mentor Graphics ModelSim
Before attempting functional simulation, ensure that the ModelSim environment is
properly configured.
Verilog
1. Navigate to the functional simulation directory:
cd <Install Path>/verilog/example/func_sim
2. Edit the test_tb.f file. This file lists command line arguments, and is shown below:
../source/glbl.v
../source/cfg_test_s.v
../source/stimulus.v
../source/test_tb.v
../source/busrec.v
../source/pcix_top.v
../source/userapp.v
../../src/xpci/pcix_lc.v
../../src/xpci/pcix_core.v
+libext+.vmd+.v
-y <Xilinx Install Path>/verilog/src/unisims
-y <Xilinx Install Path>/verilog/src/simprims
3. Modify the library search path by changing <Xilinx Install Path> to match the
Xilinx installation directory. If you have changed the wrapper file make sure you are
using the correct simulation model.
4. Save the file.