Filter
Top Products
PCI-X v5.1 165 Getting Started Guide www.xilinx.com 25
UG158 March 24, 2008
Generating Bitstreams
R
Generating Bitstreams
The bitstream generation program, bitgen, may issue DRC warnings when generating
bitstreams for PCI-X designs. The number of these warnings varies depending on the
configuration options used for the PCI-X core. Typically, these warnings are related to nets
with no loads generated during trimming by the map program. Some of these nets are
intentionally preserved by statements in the user constraints file.
Please be aware that the bitgen options provided with the example design are only for
reference. The actual options used will depend on the desired FPGA configuration method
and clock rate of your complete design, as implemented on a board. Please carefully
consider the following configuration time requirements when selecting a configuration
method and clock rate.
1. Any designs that do not automatically sense both the bus width and bus mode must be
configured within (100 ms + 2
25
bus clocks) after the bus power rails become valid.
2. Any designs that must sense either the bus width or the bus mode must be configured
within 100 ms after the bus power rails become valid.
3. Cardbus designs must be configured as quickly as possible after the bus power rails
become valid.