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Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 33
3 INSTRUCTION SET
AND r,i Logical AND immediate data i with r-register
AND r,i
r ← r ∧ i
3 to i0
110010r1 r0 i3 i2 i1 i0 C80H to CBFH
II
7
Not affected
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Performs a logical AND operation between immediate data i and the contents of
the r-register. The result is stored in the r-register.
AND A,5 AND MX,3
A register 0110 0100 0100
Memory (MX) 1000 1000 0000
C flag 1 1 1
Z flag 0 0 1
AND r,q Logical AND q-register with r-register
AND r,q
r ← r ∧ q
10101100r1 r0 q1 q0 AC0H to ACFH
IV
7
Not affected
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Performs a logical AND operation between the contents of the q-register and the
contents of the r-register. The result is stored in the r-register.
AND MX,A AND B,MY
A register 0100 0100 0100
B register 1011 1011 0010
Memory (MX) 1010 0000 0000
Memory (MY) 0010 0010 0010
C flag 0 0 0
Z flag 0 1 0