Filter
Top Products
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
74 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
RETS Return then skip an instruction
RETS
PCSL ← M(SP), PCSH ← M(SP+1), PCP ← M(SP+2), SP ← SP + 3, PC ← PC + 1
11111101 1 110 FDEH
VI
12
Not affected
Not affected
Not affected
Not affected
Jumps to the return address that was pushed onto the stack when the subroutine
was called and then skips one instruction.
RETS
PCP 0110 0000
PCS 1001 0000 0000 0111
SP B0 B3
Memory (SP)
0110 0110
Memory (SP+1)
0000 0000
Memory (SP+2)
0000 0000
RLC r Rotate r-register left with carry
RLC r
d
3 ← d2, d2 ← d1, d1 ← d0, d0 ← C, C ← d3
10101111 r1 r0 r1 r0 AF0H to AFFH
IV
7
Set when the high-order bit of the r-register is 1; otherwise, reset.
Not affected
Not affected
Not affected
Shifts the contents of the r-register one bit to the left. The high-order bit is shifted
into the carry flag and the carry bit becomes the low-order bit of the r-register.
RLC A
A register 0011 0111
C flag 1 0
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
d3 d2 d1 d0
r-register
C
C
d
2 d1 d0
r-register
C
C
d3