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Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 47
3 INSTRUCTION SET
LD A,Mn Load memory into A-register
LD A,Mn
A ← M(n
3 to n0)
11111010n
3 n2 n1 n0 FA0H to FAFH
IV
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by Mn into the A-
register.
LD A,M5 LD A,M6
A register 0100 1111 0100
Memory (05H) 1111 1111 1111
Memory (06H) 0100 0100 0100
LD B,Mn Load memory into B-register
LD B,Mn
B ← M(n
3 to n0)
11111011n
3 n2 n1 n0 FB0H to FBFH
IV
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by Mn into the B-
register.
LD B,M7 LD B,M8
B register 0100 0110 1010
Memory (07H) 0110 0110 0110
Memory (08H) 1010 1010 1010